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ISC (Science) ISC Class 12 - CISCE Important Questions

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The compliment of the Boolean expression Aꞌ • (B • Cꞌ + Bꞌ • C).

Appears in 1 question paper
Chapter: [1] Boolean Algebra
Concept: DeMorgan’S Law/Theorem and Their Applications

According to the Principle of duality, the Boolean equation (Aꞌ + B) • (1 + B) = Aꞌ + B will be equivalent to ______.

Appears in 1 question paper
Chapter: [1] Boolean Algebra
Concept: Basic Theorems of Boolean Algebra (Eg. Duality, Idempotence, Commutativity, Associativity, Distributivity, Operations with 0 and 1, Complements, Absorption, Involution)

Distributive law states that ______.

Appears in 1 question paper
Chapter: [1] Boolean Algebra
Concept: Basic Theorems of Boolean Algebra (Eg. Duality, Idempotence, Commutativity, Associativity, Distributivity, Operations with 0 and 1, Complements, Absorption, Involution)

The complement of the reduced expression of F(A,B) = ∑ (0,1,2,3) is ______.

Appears in 1 question paper
Chapter: [1] Boolean Algebra
Concept: Reducing Boolean Expression (SOP and POS) to Its Minimal Form

Study the given propositions and the statements marked Assertion and Reason that follow it. Choose the correct option on the basis of your analysis.

p = I am a triangle

q = I am a three-sided polygon

s1 = p → q

s2 = q → p

Assertion: s2 is converse of s1

Reason: Three-sided polygon must be a triangle.

Appears in 1 question paper
Chapter: [1] Boolean Algebra
Concept: Propositional Logic

A shopping mall announces a special discount on all its products as a festival offer only to those who satisfy any one of the following conditions.

  • If he/she is an employee of the mall and has a service of more than 10 years.
                                     OR
  • A regular customer of the mall whose age is less than 65 years and should not be an employee of the mall.
                                     OR
  • If he/she is a senior citizen but not a regular customer of the mall.

The inputs are:

INPUTS  
E Employee of the mall
R Regular customer of the mall
S Service of the employee is more than 10 years
C Senior citizen of 65 years or above

(In all the above cases, 1 indicates yes and 0 indicates no.)

Output: X - Denotes eligible for discount [1 indicates YES and 0 indicates NO in all cases]

Draw the truth table for the inputs and outputs given above and write the SOP expression for X ( E, R, S, C ).

Appears in 1 question paper
Chapter: [1] Boolean Algebra
Concept: Reducing Boolean Expression (SOP and POS) to Its Minimal Form

Reduce the above expression X ( E, R, S, C ) by using 4-variable Karnaugh map, showing the various groups (i.e. octal, quads and pairs).

Draw the logic gate diagram for the reduced expression. Assume that the variables and their complements are available as inputs.

Appears in 1 question paper
Chapter: [1] Boolean Algebra
Concept: Use of Karnaugh Map for Minimization of Boolean Expressions (Up to 4 Variables)

Reduce the Boolean function F(P,Q,R,S) = (P+Q+R+S) • (P+Q+R+Sꞌ) • (P+Q+Rꞌ+S) • (P+Qꞌ+R+S) • (P+Qꞌ+R+Sꞌ) • (P+Qꞌ+Rꞌ+S) • (P+Qꞌ+Rꞌ+Sꞌ) •(Pꞌ+Q+R+S) • (Pꞌ+Q+R+Sꞌ) by using 4-variable Karnaugh map, showing the various groups (i.e. octal, quads and pairs).

Appears in 1 question paper
Chapter: [1] Boolean Algebra
Concept: Use of Karnaugh Map for Minimization of Boolean Expressions (Up to 4 Variables)

From the given logic diagram:

  1. Derive Boolean expression and draw the truth table for the derived expression
  2. If A=1, B=0 and C=1, then find the value of X.
Appears in 1 question paper
Chapter: [1] Boolean Algebra
Concept: Truth Tables

Verify if the following proposition is valid using the truth table:

(X ∧ Y) =>Z = (Y => Z) ∧ (X => Y).

Appears in 1 question paper
Chapter: [1] Boolean Algebra
Concept: Truth Tables

Differentiate between half adder and full adder. Write the Boolean expression and draw the logic circuit diagram for the SUM and CARRY of a full adder.

Appears in 1 question paper
Chapter: [2] Computer Hardware
Concept: Applications of Boolean Algebra and Logic Gates to Half Adders, Full Adders, Encoders, Decoders, Multiplexers, NAND, NOR as Universal Gates

How is Encoder different from a decoder?

Appears in 1 question paper
Chapter: [2] Computer Hardware
Concept: Applications of Boolean Algebra and Logic Gates to Half Adders, Full Adders, Encoders, Decoders, Multiplexers, NAND, NOR as Universal Gates

Draw the logic circuit for a 4 :1 multiplexer and explain its working.

Appears in 1 question paper
Chapter: [2] Computer Hardware
Concept: Elementary Logic Gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) and Their Use in Circuits

When a sequence of OR, NOT, NOR are connected in series, the logic gate obtained is ______.

Appears in 1 question paper
Chapter: [2] Computer Hardware
Concept: Applications of Boolean Algebra and Logic Gates to Half Adders, Full Adders, Encoders, Decoders, Multiplexers, NAND, NOR as Universal Gates

Idempotence Law states that ______.

Appears in 1 question paper
Chapter: [2] Computer Hardware
Concept: Applications of Boolean Algebra and Logic Gates to Half Adders, Full Adders, Encoders, Decoders, Multiplexers, NAND, NOR as Universal Gates

Draw the logic gate diagram for the reduced expression. Assume that the variables and their complements are available as inputs.

Appears in 1 question paper
Chapter: [2] Computer Hardware
Concept: Applications of Boolean Algebra and Logic Gates to Half Adders, Full Adders, Encoders, Decoders, Multiplexers, NAND, NOR as Universal Gates

Draw the logic gate diagram for 2-input OR gate using NAND gates only. Show the expression at each Step.

Appears in 1 question paper
Chapter: [2] Computer Hardware
Concept: Elementary Logic Gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) and Their Use in Circuits

Draw the logic circuit for 3:8 decoder (Octal decoder). Which multiplexer can be derived from the Octal decoder?

Appears in 1 question paper
Chapter: [2] Computer Hardware
Concept: Applications of Boolean Algebra and Logic Gates to Half Adders, Full Adders, Encoders, Decoders, Multiplexers, NAND, NOR as Universal Gates

A full adder needs five gates and those are 3 AND gates, 1 OR gate and 1 XOR gate. When a full adder is constructed using 2 half adders, it also requires 5 gates. State the names along with the quantity those gates.

Appears in 1 question paper
Chapter: [2] Computer Hardware
Concept: Elementary Logic Gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) and Their Use in Circuits

Draw the logic circuit to decode the following binary number (0001, 0101, 0111, 1000, 1010, 1100, 1110,1111) to its hexadecimal equivalents. Also, state the Hexadecimal equivalents of the given binary numbers.

Appears in 1 question paper
Chapter: [2] Computer Hardware
Concept: Applications of Boolean Algebra and Logic Gates to Half Adders, Full Adders, Encoders, Decoders, Multiplexers, NAND, NOR as Universal Gates
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