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Very Large Scale Integrated Circuits Semester 7 (BE Fourth Year) BE Biomedical Engineering University of Mumbai Topics and Syllabus

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CBCGS [2019 - current]
CBGS [2015 - 2018]
Old [2000 - 2014]

University of Mumbai Semester 7 (BE Fourth Year) Very Large Scale Integrated Circuits Revised Syllabus

University of Mumbai Semester 7 (BE Fourth Year) Very Large Scale Integrated Circuits and their Unit wise marks distribution

Units and Topics

#Unit/TopicMarks
100  Module 1 -
200  Module 2 -
300  Module 3 -
400  Module 4 -
500  Module 5 -
600  Module 6 -
 Total -
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Syllabus

100 Module 1
  • Introduction to VHDL hardware description language
  • Core features of VHDL
  • Data types
  • Concurrent and sequential statements
  • Data flow
  • Behavioral, structural architecture.
  • Architecture of Xilinx XC4000 FPGA family.
200 Module 2
  • Combinational and Sequential Logic design using VHDL.
  • Using VHDL combinational circuit design examples- multipliers, decoders and encoders, cascading comparator.
  • VHDL sequential circuit design features.
  • Implementation of counters and registers in VHDL.
300 Module 3
  • Very Large Scale Integration (VLSI) Technology Physics of NMOS, PMOS
  • Enhancement and depletion mode transistor
  • MOSFET
  • Threshold voltage
  • Flatband condition
  • Linear and saturated operation
  • FET capacitance
  • Short channel and hot electron effect.
400 Module 4
  • MOS Transistors
  • MOS transistor switches
  • Basic MOS inverter and its working
  • Types of MOS invertors viz active load nMOS inverter
  • MOSFET Inverter with EnMOS as pull up
  • MOSFET Inverter with D- nMOS as pull up
  • MOSFET Inverter with pMOS as pull up
  • cmos inverter
  • Voltage transfer characteristics
  • Noise immunity and noise margins
  • Power and area considerations
  • Parameter measurement in MOS circuits.
500 Module 5
  • Silicon Semiconductor Technology Wafer processing
  • Mask generation
  • Oxidation
  • Epitaxy growth diffusion
  • Ion implantation
  • Lithography
  • Etching
  • Metalization
  • Basic NMOS and PMOS processes.
  • Latch up in CMOS and CMOS using twin tub process.
  • Scaling of MOS circuits
  • Types of scaling and limitations of scaling.
600 Module 6
  • Design rules and Layout
  • NMOS and CMOS design rules and layout
  • Design of NMOS and CMOS inverters
  • NAND and NOR gates
  • Interlayer contacts
  • Butting and buried contacts
  • Stick diagrams
  • Layout of inverter
  • NAND and NOR gates.
  • Design of basic VLSI circuits
  • Design of circuits like multiplexer, decoder, priority encoder, Flip flops, shift registers using MOS circuits.
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