# Digital Logic Design and Analysis Semester 3 (SE Second Year) BE Computer Engineering University of Mumbai Topics and Syllabus

CBCGS [2017 - current]
CBGS [2013 - 2016]
Old [2000 - 2012]

## Syllabus

100 Number Systems and Codes
• Revision of Binary, Octal, Decimal and Hexadecimal number Systems and their conversion, Binary Addition and Subtraction (1’s and 2’s complement method), Gray Code, BCD Code, Excess-3 code, ASCII Code, Error Detection and Correction Codes.
200 Boolean Algebra and Logic Gates
• Theorems and Properties of Boolean Algebra, Standard SOP and POS form, Reduction of Boolean functions using Algebric method, K -map method (2,3,4 Variable), and QuineMcClusky Method.
• NAND-NOR Realization.
• Basic Digital Circuits:- NOT,AND,OR,NAND,NOR,EX-OR,EX-NOR Gates, Logic
• Families:- Terminologies like Propagation Delay, Power Consumption , Fan in and Fan out etc. with respect to TTL and CMOS Logic and comparison.
300 Combinational Logic Design
• Introduction, Half and Full Adder, Half and Full Subtractor, Four Bit Binary Adder, one digit BCD Adder, Four Bit Binary Subtractor (1’s and 2’s compliment method), code conversion, Multiplexers and Demultiplexers, Decoders, One bit, Two bit ,4-bit Magnitude Comparator.
400 Sequential Logic Design
• Concept of Multivibrators:- Astable, Monostable and Bistable multivibrators
• Flip Flops:- SR, D, JK, JK Master Slave and T Flip Flop, Truth Tables and Excitation Tables, Flip-flop conversion.
• Sequential circuit analysis , construction of state diagrams.
• Counters:- Design of Asynchronous and Synchronous Counters, Modulo Counters, UP- DOWN counter.
• Shift Registers:- SISO, SIPO,PIPO,PISO, Bidirectional Shift Register, Universal Shift Register, Ring and Johnson Counter.
• Pseudorandom sequence generator.
500 VHDL, CPLD and FPGA
• Functional Simulation , Timing Simulation, Logic synthesis
• Introduction to VHDL, Framework of VHDL program (Syntax and programming to be done only during Practicals)
• Introduction to CPLD and FPGA