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Analog and Digital Integrated Circuits Semester 4 (SE Second Year) BE Electrical Engineering University of Mumbai Topics and Syllabus

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CBCGS [2017 - current]
CBGS [2013 - 2016]
Old [2000 - 2012]

University of Mumbai Semester 4 (SE Second Year) Analog and Digital Integrated Circuits Revised Syllabus

University of Mumbai Semester 4 (SE Second Year) Analog and Digital Integrated Circuits and their Unit wise marks distribution

Units and Topics

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Syllabus

100 Operational Amplifiers: Fundamentals
  • Basics of an Op-amp, Op-amp parameters, Frequency response
200 Application of Operational Amplifiers
  • Voltage follower, design of inverting and non- inverting amp, adder, subtractor, integrator and differentiator, V to I and I to V converter, precision rectifier, Schmitt trigger, sample and hold circuits, clipping and clamping, active filters: LP, HP and BP, Instrumentation amplifier, Optical isolation amplfier
  • Linear Voltage Regulators - IC -78xx, 79xx, LM 317. Design of adjustable voltage source using IC- LM317, Low Dropout (LDO) voltage regulator
300 Analog-to-digital Converter
  • Characteristics and types of ADC – i) Successive approximation, ii) Flash ADC, iii) Dual slope, Serial ADC Basics of Digital to Analog converter (DAC)
400 Logic Families
  • Review of Number formats: Binary, hexadecimal, BCD and their basic math operations like addition and subtraction Introduction to Logic gates and Boolean Algebra Specifications of Digital IC, Logic
  • Families: TTL, TTL variant families: like standard, LS, HS, Tristate gate, CMOS logic, Comparison of logic families, Interfacing of TTL and CMOS different families
500 Combinational Logic Circuit
  • K-Maps and their use in specifying Boolean expressions upto 4 variables, Minterm, Maxterm, SOP and POS implementation Implementing logic function using universal gates, Binary Arithmetic circuits: Adders, Subtractors (Half and Full), BCD adder – Subtractor, Carry look ahead adder, Serial adder, Multiplier Magnitude comparators, Designing code converter circuit e.g binary to gray, BCD to Seven segment parity generator, Arithmetic Logic units. Multiplexer (ULM), Shannon’s theorem, De- multiplexers, Designing using ULMS. Hazards in combinational circuits.
600 Sequential Logic Circuits
  • Comparison of combinational & sequential circuit
  • Flip-flops:SR, T, D, JK, Master Slave JK, Converting one flip-flop to another, Use of debounce switch
  • Counters: Modulus of counter, Design of Synchronous, Asynchronous counters, Ripple counters, Up/Down Counter, Ring counter, Johnson counter, Sequence generator. Unused states and locked conditions. Shift Registers
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