Discuss in Brief the Members of X-86 Family Begining from 80386 And Upwards. - Computer Science 2


Discuss in brief the members of X-86 Family begining from 80386 and upwards.



80386 :
(1) The INTEL’s 80386 is a 32-bit microprocessor introduced in 1985.
(2) 80386 is a logical extension of 80286. It is more highly pipelined.
(3) The instruction set of 80386 is a superset of other members of 8086 family.
(4) It has 32-bit data bus and 32-bit nonmultiplexed address bus. It can address a physical memory of 232 i.e. 4 Gbytes. The 80386 memory mangement allows it to  address 246 or 64 Tbytes.
(5) The 386 can be operated in one of the following memory management modes:
(a) Paged mode
(b) Non- paged mode.

(6) When operated in paged mode, the 386 switches the paging unit then after the segment unit.
The paging unit allows memory pages of 4 KB each to be swapped in and out from disk. In non -
paged mode, memory mangement unit operates very similar to the 286.
(7) Virtual addresses are represented with selected components and an offset component as they
are with 80286.
(IV) 80486 :
(1) Intel’s 80486 is a 32-bit microprocessor. It was introduced in 1989.
(2) It has 32-bit address bus and 32-bit data bus.
(3) The 486 is basically a large integral circuit which contains a fast built-in, a math coprocessor, a memory mangement unit (M.M.U), and an 8 kbyte cache memory.
(4) 80486 has DX and SX versions.
(5) All 486 processor have 32-bit data bus. SX version does not have on chip- numeric coprocessor.
(6) The 486 achieves its high speed operation from its faster clock speeds, internal pipe lined architecture and the use of reduced instruction set computing (RISC) to speed up the internal microcode.
(7) 486 also has 486 DX2 and 486 DX4 versions, with double and triple clock speed.
(V) Pentium or 80586 :
(1) Pentium is a 64 bit microprocessor, introduced in 1993.
(2) It has 64 bit data bus and 32-bit address bus. The use of super scalar architecture incorporates a dual- pipe lined processor, which lets and Pentium process more than one instruction per clock cycle. 
(3) The addition both of data and code caches on chip is also a feature designed to improve processing speed.
(4) A new advanced computing technique used in Pentium is called the brach prediction, the Pentium makes an educated guess where the next instruction following a conditional instruction will be. This prevents instruction cache from running dry during conditional instructions.
(5) The pentium has 64-bit data bus. This means that it can perform data transfers with an external device twice as fast as a processor with a 32 bit data bus.

Concept: Introdcution to Intel X-86 Family
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2015-2016 (March)



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